The present invention relates to memory matrices in general and more particularly to electronically programmable memory matrices.
From the technical journal "Electronics" of Feb. 28, 1980, pp. 113 through 117, there is known an electrically programmable memory matrix comprising programmable memory cells arranged in m columns and n rows. Each of the memory cells contains a source-drain series arrangement of a memory transistor with a select transistor. In the conventional memory matrix, there is used a memory transistor comprising an electrically floating electrode (floating gate) which, by tunnelling electrons through a thin oxide layer between the substrate and the electrically floating electrode, can be recharged as a storage medium.
From the "1980 IEEE International Solid-State Circuits Conference, Digest of Technical Papers", pp. 152 and 153 there is known a memory matrix comprising the aforementioned types of memory cells which are arranged in memory groups of b memory cells each. The memory groups, in turn, are organized in w blocks of b columns and n rows. The gates of the w . b=m select transistors of each row are connected, via a column row selecting line, to each time one of n outputs of a row decoder. The control gates of the b memory transistors of each group, however, are connected to a common programming line and, via the source-drain line of a group select transistor, are connected in blocks to a common block line. The gate of the group select transistor is connected to the corresponding row select line. Accordingly, a blockwise selection of the groups of each block becomes possible.
Moreover, in the conventional type of electrically erasable memory matrix, the memory cells are connected by columns to each time one throughgoing first and second bit line, and the block line is connected to one block signal source per block, via the source-drain line of a block select transistor whose gate is connected to one of w outputs of a block decoder. Moreover, the outputs of the block decoder are connected to the gates of b column select transistors whose source-drain lines, in turn, each time connect one of the second bit lines of each block to one of the data lines.
In the conventional memory matrix of this type the first bit lines are capable of being connected to a ground potential either low-ohmically according to the chosen function "erasing" or high-ohmically according to the function "writing". On the other hand, the second bit lines are capable of being connected to the ground potential during "erasing", or to a potential sufficiently high in relation to the ground potential during the "writing" operation, or are capable of being connected to the read potential during the "reading" operation. For the "erasing" and the "writing" operation, the gates of the select transistors are capable of being connected to the programming potential.
The invention relates to a memory matrix in which there is provided at least one of the aforementioned decoders (block decoder or row decoder). Such a memory matrix is suitable for use with equipment in which, according to the intended use, a portion of the memory cells is available for reprogramming by the user while another portion, may be used for storing company-owned balancing or other proprietary data. Yet, in the conventional memory matrix and associated circuitry of the above described type, the user is able to access even the latter portion of the memory matrix for reprogramming the same, which is quite disadvantageous since such reprogramming, whether intentional or inadvertent, could wreak havoc in the operation of the equipment.